library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity Instr_reg is
generic( numBit	: integer := 32;
			opSize	: integer := 6;
			regSize	: integer := 5);
port( clock		: in  std_logic;
		reset		: in  std_logic;
		enable	: in  std_logic;
		data_in 	: in  std_logic_vector (numBit-1 downto 0);
		opcode 	: out std_logic_vector (opSize-1 downto 0);
		r_s 		: out std_logic_vector (regSize-1 downto 0);
		r_t 		: out std_logic_vector (regSize-1 downto 0);
		r_d 		: out std_logic_vector (regSize-1 downto 0);
		Imm 		: out std_logic_vector (numBit/2-1 downto 0);
		shamt  	: out std_logic_vector (regSize-1 downto 0);
		func  	: out std_logic_vector (opSize-1 downto 0)
);
end Instr_reg;

architecture Behavioral of Instr_reg is
signal ireg : std_logic_vector(numBit-1 downto 0);
begin
	
	REG: entity work.ffdcN(structural) generic map(numBit)
	port map (clock,reset,enable,data_in,ireg);

	opcode <= ireg (numBit-1 						  downto numBit-opSize);
	r_s 	 <= ireg (numBit-opSize-1 				  downto numBit-opSize-regSize);
	r_t 	 <= ireg (numBit-opSize-regSize-1 	  downto numBit-opSize-(2*regSize));
	r_d 	 <= ireg (numBit-opSize-(2*regSize)-1 downto numBit-opSize-(3*regSize));
	shamt  <= ireg (numBit-opSize-(3*regSize)-1 downto numBit-opSize-(4*regSize));
	func   <= ireg (opSize-1						  downto 0);
	Imm 	 <= ireg (numBit/2-1 					  downto 0);
	
end Behavioral;
